Check pointing a shift register

ABSTRACT

A hardware structure provides a way for check pointing a main shift register one or more times. The hardware structure includes an extended shift register used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point. An update history shift register has a data position for each check point which is used to store information indicating whether the extended shift register was updated. Check point generation logic derives each check point by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.

BACKGROUND

As is known to those of skill in the art, a shift register is a datastructure for recording a predetermined number, N, of data elements inorder. As a new data element is received at the shift register, theexisting data elements in the shift register are “shifted” by one dataposition to make room for the new data element and the new data elementis stored in the first data position of the shift register.

Where a shift register has only N data positions (and thus can onlystore N data elements), if the shift register already has N dataelements when it receives a new data element, the last (or oldest) dataelement is shifted out of the shift register to make room for the newdata element. The data element that is shifted out (and the informationrelated thereto) is then lost. In some cases, however, it is importantto know what a shift register looked like before it was updated orbefore a certain event occurs. In these cases a copy or snapshot of theshift register is taken and stored before the shift register is updatedor the event occurs. This process of taking and storing a snapshot ofthe shift register is called check pointing the shift register.

The embodiments described below are provided by way of example only andare not limiting of implementations which solve any or all of thedisadvantages of known methods of check pointing a shift register.

SUMMARY

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used as an aid in determining the scope of the claimed subjectmatter.

Described herein are methods and hardware structures for check pointinga main shift register one or more times. The hardware structure includesan extended shift register used to store the data elements most recentlyshifted onto the main shift register which has an extra data positionfor each check point. An update history shift register has data positioninformation for each check point which is used to store informationindicating whether the extended shift register was updated in aparticular clock cycle. A check point generation logic derives eachcheck point by selecting a subset of the data elements stored in theextended shift register based on the information stored in the updatehistory shift register.

A first aspect provides a hardware structure configured to derive one ormore check points for a main shift register having a predeterminednumber of data positions. The hardware structure includes an extendedshift register with a data position for each data position of the mainshift register and an additional data position for each check point. Thedata positions of the extended shift register store data elements mostrecently shifted onto the main shift register. An update history shiftregister has a data position for each check point and each data positionof the update history register stores information indicating whether theextended shift register was updated in a same clock cycle as aparticular check point trigger event. Check point generation logicderives each check point by selecting a subset of the data positions ofthe extended shift register based on the information stored in theupdate history shift register.

A second aspect provides a method to derive one or more check points fora main shift register having a predetermined number of data positions.The method includes storing the predetermined number of data elementsmost recently shifted onto the main shift register in a plurality ofdata positions of an extended shift register. The method stores anadditional data element for each check point in an extra data positionof the extended shift register. Information is stored indicating whetherthe extended shift register was updated in a same clock cycle as aparticular check point trigger event in a data position of an updatehistory shift register. The method derives each check point by selectinga subset of the data positions of the extended shift register based onthe information stored in the update history shift register.

The preferred features may be combined as appropriate, as would beapparent to a skilled person, and may be combined with any of theaspects of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described, by way of example, withreference to the following drawings, in which:

FIGS. 1(A)-1(D) are schematic diagrams illustrating an example globalhistory register (GHR);

FIG. 2 is a block diagram of an example three-stage instruction fetchunit pipeline that uses the GHR of FIGS. 1(A)-1(D);

FIG. 3 is a schematic diagram illustrating check pointing the GHR ofFIGS. 1(A)-1(D) after a non-branch instruction is sent to the executionunit;

FIG. 4 is a schematic diagram illustrating check pointing the GHR ofFIGS. 1(A)-1(D) after a branch instruction is sent to the executionunit;

FIGS. 5(A)-5(C) are schematic diagrams illustrating an examplerestoration buffer;

FIG. 6 is a schematic diagram illustrating an extended shift registerand an update history shift register;

FIG. 7 is a flow diagram of an example method for updating the extendedshift register and the update history shift register of FIG. 6;

FIGS. 8(A)-8(D) are schematic diagrams illustrating updating theextended shift register and the update history shift register of FIG. 6using the method of FIG. 7;

FIG. 9 is a flow diagram of an example method for obtaining the firstcheck point from the extended shift register and the update historyshift register of FIG. 6;

FIG. 10 is a flow diagram of an example method for obtaining the secondcheck point from the extended shift register and the update historyshift register of FIG. 6;

FIG. 11 is a flow diagram of an example method for obtaining the thirdcheck point from the extended shift register and the update historyshift register of FIG. 6;

FIG. 12 is a schematic diagram of the check points that are obtainedfrom an example extended shift register and an example update historyshift register in accordance with the methods of FIGS. 9 to 11;

FIGS. 13(A)-13(C) are schematic diagrams of an example restorationbuffer for restoring the extended shift register and the update historyshift register of FIG. 6;

FIG. 14 is a block diagram of an example hardware structure for checkpointing a shift register;

FIG. 15 is a schematic diagram of a circular buffer and an updatehistory shift register;

FIGS. 16(A) and 16(B) are schematic diagrams illustrating updating thecircular buffer and the update history shift register after a non-branchinstruction is sent to the execution unit;

FIGS. 17(A) and 17(B) are schematic diagrams illustrating updating thecircular buffer and the update history shift register after a branchinstruction is sent to the execution unit;

FIGS. 18(A) and 18(B) are schematic diagrams illustrating updating thecircular buffer and the update history shift register after a branchinstruction is sent to the execution unit;

FIG. 19 is a flow diagram of an example method for obtaining the firstcheck point from the circular buffer and the update history shiftregister of FIG. 15;

FIG. 20 is a flow diagram of an example method for obtaining the secondcheck point from the circular buffer and the update history shiftregister of FIG. 15;

FIG. 21 is a flow diagram of an example method for obtaining the thirdcheck point from the circular buffer and the update history shiftregister of FIG. 15;

FIG. 22 is a schematic diagram of the check points that are obtainedfrom an example circular buffer and an example update history shiftregister in accordance with the methods of FIGS. 19 to 21;

FIGS. 23(A)-23(C) are schematic diagrams of a first example restorationbuffer for restoring the update history shift register and the pointerof FIG. 15;

FIGS. 24(A)-24(C) are schematic diagrams illustrating updating thepointer of FIG. 15 in response to a conditional branch instruction beingissued to an execution unit for execution;

FIGS. 25(A)-25(C) are schematic diagrams of a second example restorationbuffer for restoring the update history shift register and the pointerof FIG. 15;

FIGS. 26(A) and (B) are schematic diagrams illustrating restoring theupdate history and the pointer of FIG. 15 using the restoration bufferof FIGS. 25(A)-25(C); and

FIG. 27 is a block diagram of an example hardware structure for checkpointing a shift register.

Common reference numerals are used throughout the figures to indicatesimilar features.

DETAILED DESCRIPTION

Embodiments of the present invention are described below by way ofexample only. These examples represent the various ways of putting theinvention into practice that are currently known to the Applicantalthough they are not the only ways in which this could be achieved. Thedescription sets forth the functions of the example and the sequence ofsteps for constructing and operating the example. However, the same orequivalent functions and sequences may be accomplished by differentexamples.

Described herein are improved methods for check pointing a main shiftregister which use a small update history shift register to keep trackof changes to the main shift register. Shift registers can be used in aprocessor for a variety of purposes. For example, a shift register canbe used to store a history of the outcome (e.g. taken or not-taken) ofthe N most recent conditional branch instructions. Such a shift registeris often referred to as a Global History Register (GHR). The improvedcheck pointing methods will be described with reference to a GHR,however, it will be evident to a person of skill in the art that a GHRis only an example shift register and the improved check pointingmethods may be applied to a variety of shift registers.

Reference is now made to FIGS. 1(A)-1(D) which illustrate an example GHR102. In this example the GHR 102 comprises eight data positions(numbered 0 to 7) 104 to 118 which are used to store an ordered list ofdata elements. In this case each data element is a predicted outcome(taken/not-taken) of a conditional branch instruction so that the GHR102 stores an ordered list of the eight most recently predicted outcomes(taken/not-taken) for a conditional branch instruction. It will beevident to a person of skill in the art that other shift registers andGHRs may have a more or fewer of data positions.

In this example, the least significant data position 104 stores the mostrecently predicted outcome of a conditional branch instruction and themost significant data position 118 stores the oldest predicted outcomeof a conditional branch instruction. However, it will be evident to aperson of skill in the art that the data within the GHR may be arrangedin another manner (e.g. the most significant data position may store themost recently predicted outcome of a conditional branch instruction).

In the example of FIGS. 1(A)-1(D) each data position 104 to 118comprises a single bit which is used to store the predicted outcome (“1”or “0”) of a conditional branch instruction. In particular, in thisexample, a one (“1”) is used to indicate that the branch was predictedto be taken and a zero (“0”) is used to indicate that the branch waspredicted to be not taken. However, it will be evident to a person ofskill in the art that other shift registers and GHRs may have adifferent number of bits per data position depending on the type of datastored.

As with any shift register, when the GHR 102 receives a new data element(e.g. bit) for insertion in the GHR 102, the existing data elements(e.g. bits) in the GHR 102 are “shifted” by one data position (e.g. bit)and the new data element is stored in the first data position. Inparticular, in FIGS. 1(A) to 1(D) when the GHR 102 receives a new dataelement for insertion in the GHR 102 the data elements in the firstseven data positions 104 to 116 are shifted by one data position to thenext seven data positions 106 to 118 respectively and the new dataelement is inserted in the first data position 104 (while any datastored in the last data position 118 would be shifted out of the GHR102).

This is illustrated in FIG. 1(A) to FIG. 1(D). For example, if the GHR102 is initially set to all zeros as shown at FIG. 1(A), when the GHR102 receives a new data element (a predicted outcome of “1”) at FIG.1(B) the data “0000000” in the first seven data positions 104 to 116 isshifted by one data position to the next seven data positions 106 to 118respectively and the new data element (e.g. the new predicted outcome of“1”) is placed in the first data position 104 so that the GHR 102contains the data “00000001”. If the GHR 102 subsequently receives a “0”to be inserted into the GHR 102 then the data in the first seven datapositions 104 to 116 is similarly shifted by one data position and thenew data element “0” is inserted in the first data position 104 so thatthe GHR contains the data “00000010” as shown at FIG. 1(C). Similarly,if the GHR 102 subsequently receives a “1” to be inserted into the GHR102 then the data in the GHR 102 is again shifted by one data positionand the new data element “1” is inserted in the first data position 104so that the GHR contains the data “00000101” as shown at FIG. 1(D).

As described above, in some cases it is important to know what a shiftregister looked like before it was updated or before a certain event.For example, where the shift register is a GHR, it may be important toknow what the GHR looked like before an instruction is sent to theexecution unit for execution. In these cases a copy or snapshot of theshift register is taken and stored to keep a picture of what the shiftregister looked like before the update or before a certain event. Thisprocess of taking and storing a snapshot of the shift register is calledcheck pointing the shift register. Accordingly, an event (e.g. sendingan instruction to the execution unit for execution) that triggers checkpointing the shift register will be referred to herein as a check pointtrigger event.

For example, as illustrated in FIG. 2, an instruction fetch unit (IFU)202 of a multi-threaded processor may implement a pipelined (i.e.multi-cycle or multi-stage) process 204 for obtaining instructions froman instruction cache (i-cache) and predicting the outcome of conditionalbranch instructions using the GHR 102. In particular, in the example ofFIG. 2, the pipelined process 204 comprises three stages—a fetch stage206, a cache stage 208 and a selection stage 210; and both the fetchstage 206 and cache stage 208 use the GHR 102. For example, in the fetchstage 206 the GHR 102 may be used to generate an index for a jumpregister cache (JRC) and during the cache stage 208 the GHR 102 may beused to generate an index for a branch history table (BHT). At the endof the process 204 the GHR 102 is updated by update logic 211 to includethe predicted outcome of any conditional branch instruction.

For the prediction method to work properly the GHR value read by anystage in the pipelined process 204 has to be invariant, meaning that nomatter what is happening in the pipeline (e.g. different threadsfetching) the GHR value has to match the best case IFU performance (e.g.one thread fetching, no gaps in the fetch etc.). However, since the GHR102 is updated and read in different cycles this will not always be thecase.

For example, since in this example the processor is multi-threaded,instructions from multiple threads may be interleaved in the pipelinedprocess 204. Therefore, if in clock cycle A, a first instructionassociated with a first thread is in the fetch stage 206, a secondinstruction associated with the first thread is in the cache stage 208,and a conditional branch instruction associated with a second thread isin the selection stage 210; in clock cycle A+1 the GHR 102 will beupdated to include the predicted outcome of the conditional branchinstruction associated with the second thread and cache stage 208 willread the updated GHR 102. However, the predicted outcome for the secondstage which is included in the updated GHR 102 is not relevant forprediction of the outcome of the first or second instruction associatedwith the first thread.

Accordingly, to ensure that the prediction method works correctly, theGHR 102 is check pointed a number of times so that different stages ofthe pipelined process 204 can use different versions of the GHR asappropriate. The different versions of the GHR may be snapshots of theGHR prior to one more check point trigger events. In this example theGHR is check pointed each time the IFU sends an instruction to theexecution unit for execution thus the check point trigger event issending an instruction to the execution unit for execution, however inother examples other check point trigger events may be used. In thisexample, the GHR is check pointed three times, but in other examples theGHR or other shift register may be check pointed fewer or more times.The result of each check point may be stored in a separate check pointregister 212, 214, 216.

Reference is now made to FIGS. 3 and 4 which illustrate check pointingthe GHR. In these examples the GHR 102 is check pointed three times andthe result of each check point is stored in a separate eight-bit checkpoint register 212, 214 and 216. The first check point register 212stores the GHR as it was one check point trigger event ago (e.g. beforethe most recent instruction was sent to the execution unit forexecution); the second check point register 214 stores the GHR as it wastwo check point trigger events ago (e.g. before the two most recentinstructions were sent to the execution unit for execution); and, thethird check point register 216 stores the GHR as it was three checkpoint trigger events ago (e.g. before the three most recent instructionswere sent to the execution unit for execution).

Upon a check point trigger event occurring (e.g. an instruction is sentto the execution unit for execution) the data in the GHR 102, the firstcheck point register 212 and the second check point register 214 arecopied to the first, second and third check point registers 212, 214 and216 respectively. Specifically, the data in the second check pointregister 214 is copied to the third check point register 216 asindicated at 302; the data in the first check point register 212 iscopied to the second check point register 214 as indicated at 304; thedata in the GHR 102 is copied into the first check point register 212 asindicated at 306; and when the instruction sent to the execution unit isa conditional branch instruction the GHR 102 is updated to include thepredicted outcome of the conditional branch instruction, otherwise nochange is made to the GHR 102. For example, in the example of FIG. 3 theinstruction sent to the execution unit (EXU) was not a conditionalbranch instruction therefore in clock cycle A+1 the GHR 102 remains thesame as in clock cycle A. In contrast, in the example of FIG. 4 theinstruction sent to the execution unit (EXU) was a conditional branchinstruction and the branch was predicted to be taken thus a “1” isshifted onto the GHR 102 in clock cycle A+1.

Referring back to FIG. 2, when a mis-prediction occurs the IFU 202restores the GHR 102 and the check point registers 212, 214 and 216 towhat they were before the mis-predicted instruction was sent to theexecution unit. To be able to restore the check point registers 212, 214and 216 after a mis-prediction, the IFU 202 stores a copy of the data inthe check point registers 212, 214 and 216 for each outstanding orin-flight conditional branch instruction (i.e. conditional branchinstructions that have been predicted, but not yet executed) in arestoration buffer 218.

Reference is now made to FIGS. 5(A)-5(C) which illustrate an examplerestoration buffer 218. In the example of FIGS. 5(A)-5(C) therestoration buffer 218 is implemented as a FIFO (First In First Out)circular buffer comprising a plurality of data positions 502 ₀ to 502 ₄each of which is used to store a copy of the three check point registersfor a particular conditional branch instruction; a read pointer 504which points to the data position 502 ₀ to 502 ₄ containing the checkpoint register values for the oldest pending or outstanding conditionalbranch instruction (i.e. the conditional branch instruction predictedthe longest ago); and a write pointer 506 which points to the next dataposition 502 ₀ to 502 ₄ to be written to.

In some cases when the IFU 202 makes a conditional branch prediction thedata in the check point registers 212, 214 and 216 is pushed onto therestoration buffer 218. In particular, the data in the check pointregisters 212, 214 and 216 is written to the data position of therestoration buffer 218 indicated by the write pointer 506 and then thewrite pointer 506 is incremented to point to the next data position. Forexample, if the restoration buffer 218 has five data positions 502 ₀ to502 ₄ and the read pointer 504 points to the first data position 502 ₀and the write pointer 506 points to the fourth data position 502 ₃ asshown in FIG. 5(A), when the IFU 202 makes a branch prediction forconditional branch instruction D then the data in the check pointregisters 212, 214 and 216, referred to as Check Point 1-D, Check Point2-D and Check Point 3-D, are stored in the fourth data position 502 ₃ asshown in FIG. 5(B) and the write pointer 506 is incremented to point tothe fifth data position 502 ₄.

When the IFU 202 receives information from the execution unit (EXU)(e.g. via restoration logic 220) indicating that a branch instructionhas been executed the data in the data position 502 ₀ to 502 ₄ pointedto by the read pointer 504 is popped off the restoration buffer 218. Inparticular, the read pointer 504 is incremented to point to the nextdata position 502 ₀ to 502 ₄. For example, if the restoration buffer 218has five data positions 502 ₀-502 ₄ and the read pointer 504 points tothe first data position 502 ₀ and the write pointer 506 points to thefifth data position 502 ₄ as shown in FIG. 5(B), when the IFU 202receives information from the EXU indicating that branch instruction Ahas been executed, then the read pointer 504 is incremented to point tothe second data position 502 ₁ as shown in FIG. 5(C)

If the IFU 202 receives an indication that a mis-prediction hasoccurred. Then the IFU 202 replaces the data in the check pointregisters 212, 214 and 216 with the data from top data position (thedata position pointed to by the read pointer 504) and then nullifies theentries in the restoration buffer 218.

The number of data positions in the restoration buffer 218 is typicallyequal to the maximum number of conditional branch instructions that canbe outstanding or in-flight at any time (i.e. conditional branchinstructions that have been predicted, but not yet executed) so that theIFU 202 is able to restore the check point registers to the proper stateif any of the outstanding conditional branch instructions wasmis-predicted. Accordingly, the number of bits required for therestoration buffer 218 is equal to N*M*C where N is the number of bitsof the GHR (and thus the number of bits for each check point register),M is the number of entries in the restoration buffer 218, and C is thenumber of check point registers. Therefore where N is equal to 8, M isequal to 16 and C is equal to 3 then the restoration buffer 218 requires384 bits.

Due to the significant amount of duplication of information between theshift register (e.g. GHR) and the check point registers, check pointinga shift register by storing a copy of the shift register after multiplecheck point trigger events is inefficient. Specifically, in clock cycleswhere a check point trigger event occurs, but the shift register is notupdated (e.g. when an instruction sent to the execution unit forexecution, but the instruction is not a conditional branch instruction)the first check point will be equal to the shift register. Even in clockcycles where a check point trigger event occurs and the shift register(e.g. GHR 102) is updated (e.g. when a conditional branch instruction issent to the execution unit for execution) the first check point willonly differ from the shift register (e.g. GHR 102) by one data element(e.g. bit).

Accordingly, the present disclosure provides efficient methods andsystems for check pointing a shift register, such as a GHR, which takesadvantage of the duplication between the shift register and the checkpoints. In these methods the main shift register is extended to record alonger history and a record of the updates to the main shift register iskept in a separate update history shift register and used to determinewhich bits of the extended shift register describe the current state ofthe main shift register and any check pointed states of the main shiftregister.

FIGS. 6-12 describe a first embodiment for check pointing a main shiftregister. In this embodiment, instead of storing a full copy of the mainshift register for each check point, as described above with referenceto FIGS. 2-5, the main shift register is extended to include an extra oradditional data position (e.g. bit) for each check point and a record ofwhether an update was made to the main shift register for each of the Cprevious check point trigger events is maintained in a separate updatehistory shift register where C is the number of check points. Thecurrent state of the main shift register and the check points can thenbe identified from the extended shift register and the update historyshift register.

FIG. 6 illustrates an example structure of extended shift register 602and update history shift register 604. In this example, the main shiftregister is a GHR, but it will be evident to a person of skill in theart that the methods and principles described herein could be equallyapplied to check point other shift registers.

The extended shift register 602 comprises N+C data positions 606 to 626,where N is the number of data positions in the main shift register and Cis the number of check points. Accordingly the extended shift register602 comprises a data position 606 to 620 for each data position in themain shift register and an additional data position 622 to 626 for eachcheck point. The extended shift register 602 is updated as describedabove with reference to FIGS. 1(A) to 1(D). In particular, when a newdata element is received at the extended shift register 602 the dataelements in the extended shift register 602 are shifted one dataposition and the new data element is inserted in the first dataposition. For example, if new a data element arrives, the data elementsin data positions 606 to 624 are shifted to data positions 608 to 626respectively and the new data element is inserted in the first dataposition 606.

The data positions 606 to 626 of the extended shift register 602 aredivided into two subsets 628 and 630. The first subset 628 comprises theN data positions holding the newest data elements (i.e. the dataelements most recently added to the main shift register) and representsthe current state of the main shift register (e.g. GHR). The secondsubset 630 comprises the C data positions holding the oldest dataelements and is used, in conjunction with the update history shiftregister 604, to identify the check points for the main shift register.

For example, where the main shift register is an 8-bit GHR (N=8) whichis to be checked pointed three times (C=3) then the extended shiftregister 602 comprises 11 bits which represent the 11 most recentlypredicted conditional branch outcomes. The first subset 628 of datapositions of the extended shift register 602 comprises the 8 mostrecently predicted conditional branch outcomes, and the second subset630 of data positions of the extended shift register 602 comprises thethree oldest predicted conditional branch outcomes (i.e. the outcomesthat were predicted the longest time ago).

The update history shift register 604 is a shift register that comprisesC data positions 632 to 636 where C is the number of check points. Eachdata positions comprises information that indicates whether the extendedshift register 602 was updated a certain number of check point triggerevents ago. In particular, the first data position 632 comprisesinformation that indicates whether the extended shift register 602 wasupdated after the last check point trigger event; the second dataposition 634 comprises information that indicates whether the extendedshift register 602 was updated two check point trigger events ago; andso on.

For example, where the main shift register is a GHR which is to be checkpointed three times (C=3) then the update history shift register 604comprises three bits which indicate which of the last three instructionssent to the execution unit were branch instructions. In particular, thefirst bit 632 indicates whether the last instruction sent to theexecution unit for execution was a conditional branch instruction (thusthe outcome was predicted and the extended shift register 602 updated);the second bit 634 indicates whether the second to last instruction sentto the execution unit for execution was a conditional branch instruction(thus the outcome was predicted and the extended shift register 602updated); and the third bit 636 indicates whether the third to lastinstruction sent to the execution unit for execution was a conditionalbranch instruction (thus the outcome was predicted and the extendedshift register 602 updated).

FIG. 7 shows an example method 700 for updating the extended shiftregister 602 and the update history shift register 604 which may beexecuted each clock cycle by update logic (not shown). The method 700begins at block 701 where the update logic determines whether a checkpoint trigger event has occurred. Where the main shift register is a GHRthe check point trigger event may be when an instruction is sent to theexecution unit for execution. However, it will be evident to a person ofskill in the art that other check point trigger events may be useddepending on the purpose and use of the shift register. If it isdetermined that a check point trigger event has occurred, then themethod 700 proceeds to block 702. If, however, it is determined that acheck point trigger event has not occurred then the method 700 ends.

At block 702, the update logic determines whether the extended shiftregister is updated in the current clock cycle. This may comprisedetermining whether there is a new data element to be shifted onto theextended shift register 602. Where the main shift register is a GHR thendetermining whether the extended shift register is updated may comprisedetermining whether the outcome of a conditional branch instruction hasbeen predicted (i.e. whether the instruction sent to the instructionunit is a conditional branch instruction).

If it is determined that the extended shift register 602 is not updatedin the current clock cycle then the method proceeds to block 704 wheredata is shifted onto the update history shift register 604 to indicatethat the extended shift register 602 was not updated. In some cases, a“0” indicates that the extended shift register 602 was not updated and a“1” indicates that the extended shift register 602 was updated. In thesecases, at block 704 a “0” is shifted onto the update history shiftregister 604. No change is made to the extended shift register 602. Forexample, if the main shift register is a GHR and the extended shiftregister 602 and update history shift register 604 are as shown in FIG.8(A), then if no branch is predicted in the current clock cycle (andthus no update to the extended shift register 602) then a “0” is shiftedon to the update history shift register 604 as shown in FIG. 8(B). Inparticular, the data elements/information in bits 0 and 1 of the updatehistory shift register 604 are shifted to bits 1 and 2 respectively anda “0” is inserted in bit 0.

If, however, it is determined that the extended shift register 602 isupdated in the current clock cycle then the method 700 proceeds toblocks 706 and 708 where data is shifted onto the update history shiftregister 604 to indicate that the extended shift register was updated,and the extended shift register 602 is updated to include the new dataelement (e.g. predicted outcome of a conditional branch instruction). Insome cases, a “0” indicates that the extended shift register was notupdated and a “1” indicates the extended shift register was updated. Inthese cases, at block 706 a “1” is shifted onto the update history shiftregister 604. For example, if the main shift register is a GHR and theextended shift register 602 and update history shift register 604 are asshown in FIG. 8(B), and a branch is predicted to be not taken then a “1”is shifted on to the update history shift register 604 and a “0” isshifted onto the extended shift register 602 as shown in FIG. 8(C).Similarly, if the main shift register is a GHR and the extended shiftregister 602 and update history shift register 604 are as shown in FIG.8(C) and a branch is predicted to be taken then a “1” is shifted ontothe update history shift register 604 and a “1” is shifted onto theextended shift register 602 as shown in FIG. 8(D).

As noted above, the check point(s) for the main shift register (e.g.GHR) may be derived from the update history shift register 604 and theextended shift register 602. In particular check point generation logic(not shown) is configured to derive each check point by selecting asubset of the data positions 606 to 626 in the extended shift register602 based on the information stored in the update history shift register604.

For example, the check point generation logic may be configured toselect a subset of the data positions 606 to 626 that is offset from thefirst subset 628 of data positions by none, one, or more than one dataposition based on the information stored in the update history shiftregister 604. The offset to be used for a particular checkpoint is basedon the number of relevant data positions (e.g. bits) of the updatehistory shift register 604 that indicate that an update was made to theextended shift register 602 in the corresponding clock cycle.

The relevant data positions (e.g. bits) of the update history shiftregister 604 for a check point is based on the level or number of thecheck point. In particular, the relevant data positions (e.g. bits) ofthe update history shift register 604 for a check point are the datapositions (e.g. bits) up to and including the level of the check point.As described above each check point represents the value or dataelements of the main shift register (e.g. GHR) a predetermined number ofcheck point trigger events ago. The level of number of the check pointis equal to the predetermined number of check point trigger events. Forexample, check point 1 represents the value or data elements of the mainshift register (e.g. GHR) one check point trigger event ago thus checkpoint 1 is a level 1 check point; and check point 3 represents the valueor data elements of the main shift register (e.g. GHR) three check pointtrigger events ago thus check point 3 is a level 3 check point.

Accordingly, the offset to be used for a particular check point is basedon the number of data positions (e.g. bits) of the update history shiftregister 604 up to and including the level of the check point. Forexample, for a level 1 check point (e.g. check point 1) only the firstdata position of the update history shift register 604 is relevant andfor a level 2 check point (e.g. check point 2) only the first two datapositions of the update history shift register 604 are relevant.Therefore for a level 1 check point (e.g. check point 1) the offset isdetermined from the information in the first data position 632 of theupdate history shift register 604; and for a level 2 check point (e.g.check point 2) the offset is determined from the information in thefirst two bits of the update history shift register 604.

The offset is then equal to the number or count of the relevant datapositions of the update history shift register 604 that indicate theextended shift register 602 was updated in the same clock cycle as thecorresponding check point trigger event. For example, if only one of therelevant positions of the update history shift register 604 comprisesinformation indicating the extended shift register 602 was updated inthe same clock cycle as the corresponding check point trigger event(e.g. is set to “1”) then the subset of data positions for the checkpoint is shifted one data position relative to the first subset 628 ofdata positions so that the check point comprises the first data positionin the second subset 630 of data positions and N−1 data positions fromthe first subset 628 of data positions; and if only two of the relevantdata positions of the update history shift register 604 compriseinformation indicating the extended shift register 602 was updated inthe same clock cycle as the corresponding check point trigger event thenthe subset of data positions for the check point is shifted two datapositions relative to the first subset 629 of data position so that thecheck point comprises the first two data positions from the secondsubset 630 of data positions and N−2 data positions from the firstsubset 628 of data positions.

FIGS. 9-11 illustrate example methods for generating first, second, andthird check points from the extended shift register 602 and updatehistory shift register 604 using these principles, as further shown inFIG. 12. In particular, FIG. 9 illustrates an example method forgenerating check point 1 from the extended shift register 602 and theupdate history shift register 604 described above. Since check point 1is a level 1 check point it is only the first bit (bit 0 or dataposition 632) of the update history shift register 604 that is relevantin determining the offset.

The method 900 beings at block 902 where it is determined whether thefirst bit (e.g. bit 0 or data position 632) of the update history shiftregister 604 is set. Where a “1” is used to indicate that the extendedshift register 602 was updated then determining whether the first bit ofthe update history shift register 604 is set may comprise determining ifthe first bit is set to 1.

If it is determined that the first bit of the update history shiftregister 604 is not set then the method 900 proceeds to block 904 wherecheck point 1 is set to data positions 0 to N−1 (the first subset 628 ofdata positions) of the extended shift register 602. If, however, it isdetermined that the first bit of the update history shift register 604is set then the method 900 proceeds to block 906 where check point 1 isset to data positions 1 to N (the first data position from the secondsubset 630+the next N−1 data positions of the first subset 628) of theextended shift register 602. Accordingly, in this case, check point 1 isoffset from the first subset of data positions by one data position.

For example, if the main shift register is an 8-bit GHR (N=8) that is tobe check pointed 3 times (C=3) and the extended shift register 602 andupdate history shift register 604 are as shown in FIG. 12 then accordingto method 900 of FIG. 9 check point 1 (indicated by numeral 1202) willbe equal to the first 8 bits (bits 0 to 7) of the extended shiftregister 602 since the first bit of the update history shift register604 is not set.

FIG. 10 illustrates an example method 1000 for generating check point 2from the extended shift register 602 and the update history shiftregister 604 described above. The method 1000 begins at block 1002 whereit is determined whether both of the first two bits of the updatehistory shift register 604 are set. If it is determined that both of thefirst two bits of the update history shift register 604 are set, themethod 1000 proceeds to block 1004 where check point 2 is generated fromthe data elements in data positions 2 to N+1. Accordingly, in this case,check point 2 is offset from the first subset 628 of data positions bytwo data positions.

If, however, it is determined that both of the first two bits of theupdate history shift register are not set, then the method 1000 proceedsto block 1006 where is it determined whether one of the first two bitsof the update history shift register 604 is set. If it is determinedthat one of the first two bits of the update history shift register isset, the method 1000 proceeds to block 1008 where check point 2 isgenerated from the data elements in data positions 1 to N. Accordingly,in this case, check point 2 is offset from the first subset 628 of datapositions by one data position.

If, however, it is determined that neither of the first two bits of theupdate history shift register 604 are set, then the method 1000 proceedsto block 1010 where check point 2 is generated from the data elements indata positions 0 to N−1 (i.e. the first subset 628 of data positions).Accordingly, in this case, check point 2 is offset from the first subset628 of data positions by zero data positions.

For example, if the main shift register is an 8-bit GHR (N=8) that is tobe check pointed 3 times (C=3) and the extended shift register 602 andupdate history shift register 604 are as shown in FIG. 12 then accordingto method 1000 of FIG. 10 check point 2 (indicated by numeral 1204) willbe equal to bits 1 to 8 of the extended shift register 602 since onlyone of the first two bits of the update history shift register 604 isset.

FIG. 11 illustrates an example method 1100 for generating check point 3from the extended shift register 602 and the update history shiftregister 604 described above. The method 1100 begins at block 1102 whereit is determined whether all of the first three bits of the updatehistory shift register are set. If it is determined that all of thefirst three bits of the update history shift register are set, themethod 1100 proceeds to block 1104 where check point 3 is generated fromthe data elements in data positions 3 to N+2. Accordingly, in this case,check point 3 is offset from the first subset 628 of data positions bythree data positions.

If, however, it is determined that all of the first three bits of theupdate history shift register 604 are not set the method 1100 proceedsto block 1106 where it is determined whether two of the first three bitsof the update history shift register are set. If it is determined thattwo of the first three bits of the update history shift register 604 areset, the method 1100 proceeds to block 1108 where check point 3 isgenerated from the data elements in data positions 2 to N+1.Accordingly, in this case, check point 3 is offset from the first subset628 of data positions by two data positions.

If, however, it is determined that less than two of the first three bitsof the update history shift register 604 are set, then the method 1100proceeds to block 1110 where it is determined whether one of the firstthree bits of the update history shift register 604 is set. If it isdetermined that one of the first three bits of the update history shiftregister 604 is set, the method 1100 proceeds to block 1112 where checkpoint 3 is generated from the data elements in data positions 1 to N.Accordingly, in this case, check point 3 is offset from the first subset628 of data positions by one data position.

If, however, it is determined that none of the first three bits of theupdate history shift register 604 are set, then the method 1100 proceedsto block 1114 where check point 3 is generated from the data elements indata positions 0 to N−1 (i.e. the first subset 628 of data positions).Accordingly, in this case, check point 3 is offset from the first subset628 of data positions by zero data positions.

For example, if the main shift register is an 8-bit GHR (N=8) that is tobe check pointed 3 times (C=3) and the extended shift register 602 andupdate history shift register 604 are as shown in FIG. 12 then accordingto method 1100 of FIG. 11 check point 3 (indicated by numeral 1206) willbe equal to bits 1 to 8 of the extended shift register 602 since onlyone of the first two bits of the update history shift register 604 isset.

When an extended shift register 602 and update history shift register604 are used to check point a main shift register (e.g. GHR), then to beable to restore the check points to a previous point in time (e.g. aftera branch mis-prediction), instead of storing a copy of all the checkpoints in a restoration buffer as described above with reference toFIGS. 5(A)-5(C), only the update history shift register 604 and theextended shift register 602 are stored in the restoration buffer foreach relevant point in time (e.g. before a conditional branchinstruction is issued to the execution unit).

Reference is now made to FIGS. 13(A)-13(C) which illustrate an examplerestoration buffer 1300 for storing the update history shift register604 and extended shift register 602 at particular points of time (e.g.before a conditional branch instruction is sent to the execution unitfor execution) to allow the main shift register (e.g. GHR) and checkpoints to be restored to that point in time (e.g. after a mis-predictionof a conditional branch instruction). Like the restoration buffer 218 ofFIGS. 5(A)-5(C) the restoration buffer 1300 is implemented as a FIFOcircular buffer comprising a plurality of data positions 1302 ₀ to 1302₄ each of which is used to store a copy of the update history shiftregister 604 and extended shift register 602 at a particular point intime (e.g. before a conditional branch instruction is issued to theexecution unit); a read pointer 1304 which points to the data position1302 ₀ to 1302 ₄ containing the update history shift register 604 andextended shift register for the oldest point in time (e.g. correspondingto the point in time before the oldest outstanding conditional branchinstruction was issued to the execution unit); and a write pointer 1306which points to the next data position 1302 ₀ to 1302 ₄ to be writtento.

Each time an update trigger event happens (e.g. IFU 202 predicts theoutcome of a conditional branch instruction) update logic (not shown)pushes the information in the update history shift register 604 and thedata elements in the extended shift register 602 onto the restorationbuffer 1300. In particular, the information in the update history shiftregister 604 and the data elements stored in the extended shift register602 are written to the data position indicated by the write pointer 1306and then the write pointer 1306 is incremented to point to the next dataposition. For example, if the restoration buffer 1300 is as shown inFIG. 13(A) when the update trigger event happens (e.g. IFU 202 predictsthe outcome for conditional branch instruction D) then the informationin the update history shift register 604 and the data elements stored inthe extended shift register 602 are stored in the data position pointedto by the write pointer 1306 and then the write pointer 1306 isincremented to point to the next data position as shown in FIG. 13(B).

Each time the update logic (not shown) receives a removal trigger (e.g.information is received from the execution unit (EXU) indicating that abranch instruction has been executed) the update logic pops off the dataelements in the data position 1302 ₀ to 1302 ₄ pointed to by the readpointer 1304 from the restoration buffer 1300. This may be done byincrementing the read pointer 1304 to point to the next data position1302 ₀ to 1302 ₄. For example, if the restoration buffer 1300 is asshown in FIG. 13(B), when a removal trigger is received (e.g.information from the EXU indicating that branch instruction A has beenexecuted is received), then the read pointer 1304 is incremented topoint to the next data position as shown in FIG. 13(C).

If restoration logic (not shown) receives a restoration trigger (e.g. anindication that a mis-prediction has occurred) then the restorationlogic replaces the information in the update history shift register 604and the data elements in the extended shift register 602 with the datafrom the top data position (the data position pointed to by the readpointer 1304) and then nullifies the entries in the restoration buffer1300.

In this example each data position in the restoration buffer 1300 has Cbits (for the update history shift register)+N+C bits (for the extendedshift register). Where there are M data positions in the restorationbuffer the total number of bits for the restoration buffer is thenM*(2C+N). So, where C is 3, N is 8 and M is 16 the total number of bitsfor the restoration buffer 1300 is 224. Accordingly check pointing ashift register using an update history shift register and an extendedshift register provides a significant cost savings in terms of storagefor the restoration buffer 1300 as compared to using the check pointingmethod described above with reference to FIGS. 1 to 5.

It will be evident to a person of skill in the art that the structure ofthe restoration buffer 1300 in FIGS. 13(A)-13(C) is an example only andthe restoration buffer may take another form (e.g. the restoration maybe implemented as an indexed buffer or table).

Reference is now made to FIG. 14 which illustrates an example hardwarestructure 1400 for implementing the shift register check pointing methoddescribed above with reference to FIGS. 6 to 13. The hardware structurecomprises the extended shift register 602, the update history shiftregister 604, and the restoration buffer 1300 described above.

The hardware structure also comprises update logic 1402 for updating theextended shift register 602, update history shift register 604, andrestoration buffer 1300 as described above. In particular, the updatelogic is configured to receive new data elements for the main shiftregister (e.g. GHR) and update the extended shift register 602, updatehistory shift register 604, and restoration buffer 1300 accordingly asdescribed with reference to FIGS. 7, 8 and 13. For example, where theshift register being check pointed is a GHR the new data elements to beadded to the GHR may be the predicted outcome of a conditional branchinstruction.

The hardware structure 1400 also comprises check point generation logic1404 for generating the check points and/or main shift register from theextended shift register 602 and the update history shift register 604 asdescribed above with reference to FIGS. 9-11. For example, the checkpoint generation logic 1404 may be configured to implement one or moreof the methods described with reference to FIGS. 9 to 11.

The hardware structure 1400 may also comprise restoration logic 1406 forreplacing the information in the extended shift register 602 and theupdate history shift register 604 with the information stored in therestoration buffer 1300 upon a restoration trigger event (e.g.mis-prediction of a conditional branch instruction) occurring asdescribed above with reference to FIGS. 13(A)-13(C).

FIGS. 15 to 26 describe a second embodiment for check pointing a shiftregister. The second embodiment, like the first embodiment (describedabove with respect to FIGS. 6 to 14), uses an update history shiftregister to keep track of which of the previous C check point triggerevents also resulted in an update to the main shift register; and anextended shift register. However, instead of the extended shift registercomprising an extra data position (e.g. bit) for each check point, theextended shift register is implemented as a circular buffer that has M+Cextra data positions where M is the number of different snapshots of theshift register and check points that can be restored (e.g. the number ofbranch instructions that can be outstanding or in-flight at any time)and C is the number of check points. Accordingly, where there can be amaximum of thirteen conditional branch instructions outstanding orin-flight at any one time (M=13), and there are three checkpoints (C=3),the circular buffer comprises 16 extra data positions.

FIG. 15 illustrates an example update history shift register 1504 andcircular buffer 1502 for check pointing a main shift register. Theupdate history shift register 1504 of FIG. 15 is the same as the updatehistory shift register 604 described above with reference to FIGS. 6 to13. In particular, it has a bit 1506 to 1510 for each check point; andin each clock cycle that a check point trigger event occurs information(e.g. a “1” or “0”) is pushed onto the update history shift register1504 indicating whether the circular buffer 1502 has been updated inthat clock cycle. Where a check point trigger event does not occur everyclock cycle then the update history shift register 1504 is not updatedin clock cycles in which a check point trigger event does not occur.

The circular buffer 1502 comprises M+C+N data positions 1512-1558 forholding the M+C+N most recent data elements added to the shift register(e.g. the most recently predicted branch instruction outcomes). Asdescribed above, M is the number of different snapshots of the mainshift register and check points that can be restored (e.g. the maximumnumber of branch instructions that can be outstanding or in-flight atany one time), C is the number of check points, and N is the size of themain shift register being check pointed.

The next data position of the circular buffer 1502 to be written to isidentified by a top pointer 1560. In particular, the top pointer 1560comprises a plurality of bits 1562 to 1570 that together form an indexthat identifies a particular data position 1512 to 1558 of the circularbuffer 1502. For example, in FIG. 15 the index formed by the bits 1562to 1570 of the top pointer 1560 is “00011” in binary which is equivalentto the decimal value three. Therefore the top pointer 1560 points todata position 3 (identified as numeral 1518). When a new data element isreceived for insertion onto the shift register the data element is addedto the data position identified by the top pointer 1560 and then the toppointer 1560 is decremented.

FIGS. 16-18 show examples of how the update history shift register 1504and circular buffer 1502 may be updated after a check point triggerevent has occurred (e.g. when an instruction is sent to the executionunit for execution). In these examples the main shift register is an8-bit GHR (N=8) that is check pointed three times (C=3); the GHR isupdated with a “1” when a branch is predicted to be taken and a “0” whena branch is predicted to be not taken; and the update history shiftregister 1504 is updated with a “1” when a conditional branchinstruction is sent to the execution unit (and thus a branch ispredicted) and is updated with a “0” when a non-conditional branchinstruction is sent to the execution unit (and thus no branch ispredicted).

FIG. 16(A) shows the update history shift register 1504 and circularbuffer 1502 when the IFU 202 sends a non-branch instruction to theexecution unit for execution. This causes a “0” to be pushed onto theupdate history shift register 1504 as shown in FIG. 16(B) to indicatethat the circular buffer 1502 was not updated for this instruction. Thecircular buffer 1502 and the top pointer are not updated.

FIG. 17(A) shows the update history shift register 1504 and circularbuffer 1502 when the IFU 202 sends a conditional branch instruction thatis predicted to be not taken to the execution unit for execution. Thiscauses a “1” to be pushed onto the update history shift register 1504 toindicate that the circular buffer 1502 was updated in this clock cycle;a “0” is inserted in data position 3 of the circular buffer 1502 toindicate that a branch was predicted not to be taken; and the toppointer 1560 is decremented to “00010” (2) as shown in FIG. 17(B).

FIG. 18(A) shows the update history shift register 1504 and circularbuffer 1502 when the IFU 202 sends a conditional branch instruction thatis predicted to be taken to the execution unit for execution. Thiscauses a “1” to be pushed onto the update history shift register toindicate that the circular buffer 1502 was updated in this clock cycle;a “1” to be inserted in data position 3 of the circular buffer 1502 toindicate that a branch was predicted to be taken; and the top pointer1560 is decremented to “00010” (2) as shown in FIG. 18(B).

Referring back to FIG. 15, in addition to indicating the next dataposition of the circular buffer to be written to, the top pointer 1560also identifies the active data positions A₁ to A₁₁ of the circularbuffer. The active data positions A₁ to A₁₁ are those data positions ofthe circular buffer from which the current values of the main shiftregister and check points can be determined. The active data positionsA₁ to A₁₁ are generally the N+C data positions preceding the dataposition indicated, or pointed to, by the top pointer 1560. Inparticular if the data position indicated, or pointed to, by the toppointer is Y then the active data positions are data positions Y+1through Y+N+3. For example, when the top pointer points to data position3 (indicated by reference numeral 1420), N=8 and C=3, then the activedata positions A₁ to A₁₁ are data positions 4 to 14 (indicated byreference numerals 1520 to 1540).

The active data positions A₁ to A₁₁ can be understood as being akin tothe data positions 606 to 626 of the extended shift register 602described above with reference to FIGS. 6 to 13. In particular, like thedata positions 606 to 626 of the extended shift register 602, the activedata positions A₁ to A₁₁ are divided into two subsets 1572 and 1574. Thefirst subset 1572 is the N active data positions A₁ to A₈ holding thenewest data elements (i.e. the data elements most recently added to thecircular buffer) and represents the current state of the main shiftregister (e.g. GHR). The second subset 1574 is the next C data positionswhich hold the next C newest data elements.

For example, where the main shift register is an 8-bit GHR (N=8) whichis to be checked pointed three times (C=3) then there are eleven activedata positions A₁ to A₁₁ which represent the 11 most recently predictedbranch outcomes. The first subset 1572 of active data positionscomprises the 8 most recently predicted branch outcomes, and the secondsubset 1574 of active data positions comprises the three next mostrecently predicted outcomes.

Accordingly, in the same way that the update history shift register 604of FIGS. 6 to 13 is used to identify the current check point values fromthe data positions 606 to 626 of the extended shift register 602 ofFIGS. 6 to 14, the update history shift register 1504 can be used toidentify the current check point values from the active data positionsA₁ to A₁₁. In particular, the update history shift register 1504identifies and/or selects the active data positions A₁ to A₁₁ whichprovide the current value for each check point.

For example, check point generation logic may be configured to select asubset of the active data positions A₁ to A₁₁ that is offset from thefirst subset 1572 of active data positions by none, one, or more thanone data position based on the information stored in the update historyshift register 1504. The offset to be used for a particular checkpointis based on the number of relevant data positions (e.g. bits) of theupdate history shift register 604 that indicate that an update was madeto the circular buffer 1502 in the same clock cycle as the correspondingcheck point trigger event.

As described above with reference to FIGS. 6 to 13, the relevant datapositions (e.g. bits) of the update history shift register 1504 for acheck point is based on the level or number of the check point. Inparticular, the relevant data positions (e.g. bits) of the updatehistory shift register 1504 for a check point are the data positions(e.g. bits) up to and including the level of the check point. Asdescribed above, each check point represents the value or data elementsof the main shift register (e.g. GHR) a predetermined number of checkpoint trigger events ago. The level or number of the check point isequal to the predetermined number of check point trigger events. Forexample, check point 1 represents the value or data elements of the mainshift register (e.g. GHR) one check point trigger event ago thus checkpoint 1 is a level 1 check point; and check point 3 represents the valueor data elements of the main shift register (e.g. GHR) three check pointtrigger events ago thus check point 3 is a level 3 check point.

Accordingly, the offset to be used for a particular check point is basedon the number of data positions (e.g. bits) of the update history shiftregister 1504 up to and including the level of the check point. Forexample, for a level 1 check point (e.g. check point 1) only the firstdata position of the update history shift register 1504 is relevant andfor a level 2 check point (e.g. check point 2) only the first two datapositions of the update history shift register 1504 are relevant.Therefore for a level 1 check point (e.g. check point 1) the offset isdetermined from the information in the first data position 1506 of theupdate history shift register 1504; and for a level 2 check point (e.g.check point 2) the offset is determined from the information in thefirst two data positions of the update history shift register 1504.

The offset is then equal to the number or count of the relevant datapositions of the update history shift register 1504 that compriseinformation indicating the circular buffer 1502 was updated in the clockcycle of the corresponding check point trigger event (e.g. is set to“1”) then the subset of active data positions for the check point isshifted one data position relative to the first subset 1572 of activedata positions so that the check point comprises the first data positionin the second subset 1574 of active data positions and N−1 datapositions from the first subset 1572 of active data positions; and ifonly two of the relevant data positions of the update history shiftregister 1504 comprise information indicating the circular buffer 1502was updated in the clock cycle for the corresponding check point triggerevent (e.g. is set to “1”) then the subset of active data positions forthe check point is shifted two data positions relative to the firstsubset 1572 of active data positions so that the check point comprisesthe first two data positions from the second subset 1574 of active datapositions and N−2 data positions from the first subset 1572 of activedata positions.

FIGS. 19-21 illustrate example methods for generating first, second, andthird check points from the circular buffer 1502 and the update historyshift register 1504 using the principles described above in relation tothe extended shift register 602 and update history shift register 604.In particular, FIG. 19 illustrates an example method 1900 for generatingcheck point 1 from the circular buffer 1502 and the update history shiftregister 1504 described above. Since check point 1 is a level one checkpoint it is only the first bit (bit 0 or data position 1506) of theupdate history shift register 1504 that is used to determine therelevant bits from the circular buffer 1502.

The method 1900 beings at block 1902 where it is determined whether thefirst bit (e.g. bit 0 or data position 1506) of the update history shiftregister 1504 is set. Where a “1” is used to indicate that the circularbuffer 1502 was updated in the clock cycle for the corresponding checkpoint trigger event, determining whether the first bit of the updatehistory shift register 1504 is set may comprise determining if the firstbit is set to 1.

If it is determined that the first bit of the update history shiftregister 1504 is not set then the method 1900 proceeds to block 1904where check point 1 is set to the data elements in active data positionsA₁ to A_(N) (the first subset 1572 of active data positions) of thecircular buffer 1502. If, however, it is determined that the first bitof the update history shift register 1504 is set then the method 1900proceeds to block 1906 where check point 1 is set to the data elementsin active data positions A₂ to A_(N+1) (the first active data positionfrom the second subset 1574+the next N−1 active data positions in thefirst subset 1572). Accordingly, in this case, check point 1 is offsetfrom the first subset of active data positions by one data position.

For example, if the main shift register is an 8-bit GHR (N=8) that is tobe check pointed 3 times (C=3) and the circular buffer 1502 and theupdate history shift register 1504 are as shown in FIG. 22 thenaccording to method 1900 of FIG. 19 check point 1 (indicated byreference numeral 2202) will be equal to the data in active data bits A₂to A₉ of the circular buffer 1502 since the first bit of the updatehistory shift register 1504 is set.

FIG. 20 illustrates an example method 2000 for generating check point 2from the circular buffer 1502 and the update history shift register 1504described above. The method 2000 begins at block 2002 where it isdetermined whether both of the first two bits of the update historyshift register 1504 are set. If it is determined that both of the firsttwo bits of the update history shift register 1504 are set, the method2000 proceeds to block 2004 where check point 2 is generated from thedata elements in active data positions A₃ to A_(N+2).

Accordingly, in this case, check point 2 is offset from the first subset1572 of active data positions by two data positions.

If, however, it is determined that both of the first two bits of theupdate history shift register 1504 are not set, then the method 2000proceeds to block 2006 where is it determined whether one of the firsttwo bits of the update history shift register is set. If it isdetermined that one of the first two bits of the update history shiftregister are set, the method 2000 proceeds to block 2008 where checkpoint 2 is generated from the data elements in active data positions A₂to A_(N+1). Accordingly, in this case, check point 2 is offset from thefirst subset 1572 of active data positions by one data position.

If, however, it is determined that none of the first two bits of theupdate history shift register 1504 are set, then the method 2000proceeds to block 2010 where check point 2 is generated from the dataelements in active data positions A₁ to A_(N) (i.e. the first subset1572 of data positions). Accordingly, in this case, check point 2 isoffset from the first subset 1572 of active data positions by zero datapositions.

For example, if the main shift register is an 8-bit GHR (N=8) that is tobe check pointed 3 times (C=3) and the circular buffer 1502 and updatehistory shift register 1504 are as shown in FIG. 22 then according tomethod 2000 of FIG. 20 check point 2 (indicated by numeral 2204) will beequal to the active data positions A₂ to A₉ of the circular buffer 1502since only one of the first two bits of the update history shiftregister 1504 is set.

FIG. 21 illustrates an example method 2100 for generating check point 3from the circular buffer 1502 and the update history shift register 1504described above. The method 2100 begins at block 2102 where it isdetermined whether all of the first three bits of the update historyshift register 1504 are set. If it is determined that all of the firstthree bits of the update history shift register 1504 are set, the method2100 proceeds to block 2104 where check point 3 is generated from thedata elements in active data positions A₄ to A_(N+3). Accordingly, inthis case, check point 3 is offset from the first subset 1572 of activedata positions by three data positions.

If, however, it is determined that not all of the first three bits ofthe update history shift register 1504 are set the method 2100 proceedsto block 2106 where it is determined whether two of the first three bitsof the update history shift register 1504 are set. If it is determinedthat two of the first three bits of the update history shift register1504 are set, the method 2100 proceeds to block 2108 where check point 3is generated from the data elements in active data positions A₃ toA_(N+2). Accordingly, in this case, check point 3 is offset from thefirst subset 1572 of active data positions by two data positions.

If, however, it is determined that less than two of the first three bitsof the update history shift register 1504 are set, then the method 2100proceeds to block 2110 where is it determined whether one of the firstthree bits of the update history shift register 1504 is set. If it isdetermined that one of the first three bits of the update history shiftregister 1504 is set, the method 2100 proceeds to block 2112 where checkpoint 3 is generated from the data elements in active data positions A₂to A_(N+1). Accordingly, in this case, check point 3 is offset from thefirst subset 1572 of active data positions by one data position.

If, however, it is determined that none of the first three bits of theupdate history shift register 1504 are set, then the method 2100proceeds to block 2114 where check point 3 is generated from the dataelements in active data positions A₁ to A_(N) (i.e. the first subset1572 of active data positions).

For example, as shown in FIG. 22, if the main shift register is an 8-bitGHR (N=8) that is to be check pointed 3 times (C=3) and the circularbuffer 1502 and update history shift register 1504 are as shown thenaccording to method 2100 of FIG. 21 check point 3 (indicated by numeral2206) is generated from bits A₃ to A₁₀ of the circular buffer 1502 sinceonly two of the first three bits of the update history shift register1504 are set.

Using a circular buffer 1502 and an update history shift register 1504to check point a main shift register (e.g., GHR) as described above withreference to FIGS. 15 to 22 significantly reduces the amount of datathat needs to be stored to be able to restore the main shift register(e.g. GHR) and check points to a previous point in time (e.g. after amis-prediction of a conditional branch instruction). Specifically,instead of storing a copy of all the check points in a restorationbuffer for each relevant point in time (e.g. before each outstandingconditional branch instruction was issued to the execution unit) asdescribed above with reference to FIGS. 5(A)-5(C), only the updatehistory shift register 1504 and the top pointer 1560 are stored in therestoration buffer for each relevant point in time (e.g. before eachoutstanding conditional branch instruction is issued to the executionunit). Since the circular buffer 1502 contains N+M+C predicted outcomesit contains enough predicted outcomes that the main shift register (e.g.GHR) and associated check points for any outstanding conditional branchinstruction can be recovered from the current circular buffer 1502itself and does not require storing a copy of the circular buffer 1502.

FIGS. 23(A)-23(C) illustrate a first example of a restoration buffer2300 for restoring the main shift register and check points to aprevious point in time. In this example the restoration buffer 2300 isconfigured to store the information in the update history shift register1504 and the value of the top pointer 1560 for a relevant point in time(e.g. before a conditional branch instruction is sent to the executionunit for execution). Like the restoration buffers 218 and 1300 of FIGS.5 and 13, the restoration buffer 2300 is implemented as a FIFO circularbuffer which has a plurality of data positions 2302 ₀ to 2302 ₄ each ofwhich is used to store a copy of the information in the update historyshift register 1504 and top pointer 1560 for a particular point in time(e.g. before a conditional branch instruction is sent to the executionunit for execution); a read pointer 2304 which points to the dataposition 2302 ₀ to 2302 ₄ containing the information in the updatehistory and value of the top pointer for the oldest relevant point intime (i.e. before the oldest pending conditional branch instruction wassent to the execution unit for execution); and a write pointer 2306which points to the next data position 2302 ₀ to 2302 ₄ to be writtento.

Each time an update trigger event occurs (e.g. a conditional branchinstruction is issued to the execution unit) the information in theupdate history shift register 1504 and the value of the top pointer 1560are pushed onto the restoration buffer 2300. In particular, theinformation in the update history shift register 1504 and the value ofthe top pointer 1560 are written to the data position indicated by thewrite pointer 2306 and then the write pointer 2306 is incremented topoint to the next data position. For example, if the restoration buffer2300 is as shown in FIG. 23(A) when an update trigger even occurs (e.g.a conditional branch instruction D is sent to the execution unit forexecution) then the information in the update history shift register1504 and the value of the top pointer 1560 are stored in the dataposition pointed to by the write pointer 2306 and then the write pointer2306 is incremented to point to the next data position as shown in FIG.23(B).

Each time a removal trigger event occurs (e.g. information from theexecution unit (EXU) indicating that a conditional branch instructionhas been executed is received) the data elements in the data position2302 ₀ to 2302 ₄ pointed to by the read-pointer 2304 are popped off therestoration buffer 2300. This may be done by incrementing the readpointer 2304 to point to the next data position 2302 ₀ to 2302 ₄. Forexample, if the restoration buffer 2300 is as shown in FIG. 23(B), whena removal trigger event occurs (e.g. information is received from theEXU indicating that branch instruction A has been executed), then theread pointer 2304 is incremented to point to the next data position asshown in FIG. 23(C).

When a restoration trigger event occurs (e.g. an indication that amis-prediction has occurred is received) then the information in theupdate history shift register 1504 and value of the top pointer 1560 arereplaced with the data from the top data position (the data positionpointed to by the read pointer 2304) and the entries in the restorationbuffer 2300 are nullified. This causes the active data positions of thecircular buffer 1502 to be altered so that a different set of datapositions of the circular buffer 1502 are used to determine the currentvalue of the main shift register (e.g. GHR) and check points. In otherwords it moves the active data positions back to what they were at theprevious point in time (e.g. before the mis-predicted branch instructionwas issued to the execution unit for execution).

In this example each data position in the restoration buffer 2300 has Cbits (for the update history shift register)+K bits (for the toppointer). Where there are M data positions in the restoration buffer thetotal number of bits for the restoration buffer is then M*(C+K). So,where C is 3, K is 5 and M is 16 the total number of bits to implementthe restoration buffer 2300 is 128. Accordingly this provides asignificant cost savings in terms of storage for the restoration buffer2300 as compared to check pointing a shift register using the methoddescribed above with reference to FIGS. 1 to 5 or the method describedabove with reference to FIGS. 6 to 13.

In other examples, instead of storing the value of the top pointer 1560at a particular point in time in the restoration buffer, informationenabling the top pointer 1560 to be restored to a particular point intime can be stored in the restoration buffer. As described above, thetop pointer 1560 is adjusted (e.g. decremented) each time a new elementis added to the circular buffer 1502. For example, where the main shiftregister is a GHR, a new element will be added to the circular buffer1502 (and thus the top pointer 1560 updated) each time the outcome of aconditional branch instruction is predicted (e.g. each time aconditional branch instruction is sent to the execution unit forexecution). Accordingly, if the number of circular buffer updates (e.g.conditional branch instructions sent to the execution unit) that haveoccurred since the particular point in time is known the top pointer atthat particular time can be generated by adjusting (e.g. incrementing)the top pointer 1560 by that number. For example, if two new elementshave been added to the circular buffer after a particular point in time(e.g. after a particular instruction has been sent to the executionunit), the top pointer has been decremented twice since that point intime. Accordingly, the top pointer can be restored to that particularpoint in time by incrementing the top pointer by two.

This concept is illustrated using the example of FIGS. 24(A)-24(C). Inthis example the main shift register is a GHR which is updated after aconditional branch instruction (for which a prediction of whether thebranch is taken or not taken is made) is sent to the execution unit forexecution. As shown in FIG. 24(A) the update history shift register 1504is equal to “001”, the top pointer 1560 is equal to “00011” (3), and thecircular buffer 1502 is equal to “010100000100101100011101” meaning thatthe active data positions A₀ to A₁₁ of the circular buffer are datapositions 4 to 14 of the circular buffer 1502.

If the IFU 202 subsequently sends a conditional branch instruction(instruction X) in which the branch predicted to be taken to theexecution unit for execution, a “1” is pushed onto the update historyshift register 1504 to indicate that the circular buffer 1502 wasupdated in this clock cycle; a “1” is inserted in data position 3 of thecircular buffer 1502 to indicate that a branch was predicted to betaken; and the top pointer 1560 is decremented by one to “00010” (2) asshown in FIG. 24(B).

If the IFU 202 subsequently sends a conditional branch instruction(instruction X+1) in which the branch is predicted not to be taken tothe execution unit for execution, a “1” is pushed onto the updatehistory shift register 1504 to indicate that the circular buffer 1502was updated in this clock cycle; a “0” is inserted in data position 2 ofthe circular buffer 1502 to indicate that a branch was predicted not tobe taken; and the top pointer 1560 is decremented by one to “00001” (1)as shown in FIG. 24(C).

If it is then determined that instruction X was mis-predicted then theupdate history 1504 and the top pointer 1560 are restored to the pointin time before instruction X was sent to the execution unit forexecution (i.e. the point in time shown in FIG. 24(A)). Since twoconditional branch instructions (instruction X and instruction X+1) weresent to the execution unit since the point in time shown in FIG. 24(A)the circular buffer 1502 was updated twice and thus the top pointer 1560was decremented twice. The top pointer 1560 can thus be restored to thepoint in time shown in FIG. 24(A) by incrementing the top pointer 1560of “00001” (1) of FIG. 24(C) by two to set the top pointer 1560 back to“00011” (3). Accordingly, the top pointer 1560 can be restored to aparticular point in time by keeping track of the number of times thecircular buffer was updated after that point in time.

FIGS. 25(A)-25(C) illustrate a second example restoration buffer 2500for restoring the main shift register and check points to a previouspoint in time. In this example the restoration buffer 2500 is configuredto store the information in the update history shift register 1504 at aparticular point in time (e.g. before a control transfer instruction(CTI)—an instruction that changes the direction of the program (e.g. abranch instruction, jump instruction)—is sent to the execution unit forexecution) and an indication of whether the circular buffer 1502 wasupdated in that clock cycle. The indication of whether the circularbuffer 1502 was updated may also be referred to herein as the circularbuffer update indication. Where the main shift register is a GHR thenthe indication of whether the circular buffer 1502 was updated is set toindicate the circular buffer 1502 was updated when a conditional branchinstruction was sent to the execution unit (and thus a prediction ismade of whether the branch is taken).

Like the restoration buffers 218, 1300 and 2300 of FIGS. 5, 13 and 23,the restoration buffer 2500 of FIGS. 25(A)-25(C) is implemented as aFIFO circular buffer which has a plurality of data positions 2502 ₀ to2502 ₄ each of which is used to store a copy of the information in theupdate history shift register 1504 at a particular point in time (e.g.before a control transfer instruction (CTI), such as conditional branchinstruction or a direct branch instruction is sent to the execution unitfor execution) and an indication of whether the circular buffer wasupdated (e.g. whether the instruction sent to the execution unit was aconditional branch instruction); a read pointer 2504 which points to thedata position 2502 ₀ to 2502 ₄ containing the information in the updatehistory and the circular buffer update indication for the oldestrelevant point in time (i.e. before the oldest pending control transferinstruction was sent to the execution unit for execution); and a writepointer 2506 which points to the next data position 2502 ₀ to 2502 ₄ tobe written to.

Each time an update trigger event occurs (e.g. a control transferinstruction, such as a conditional branch instruction or a jumpinstruction, is sent to the execution unit for execution) theinformation in the update history shift register 1504 and an indicationof whether the circular buffer 1502 was updated (e.g. whether thecontrol transfer instruction is a conditional branch instruction) arepushed onto the restoration buffer 2500. In particular, the informationin the update history shift register 1504 and an indication of whetherthe circular buffer was updated are written to the data positionindicated by the write pointer 2506 and then the write pointer 2506 isincremented to point to the next data position. For example, if therestoration buffer 2500 is as shown in FIG. 25(A) when an update triggereven occurs (e.g. conditional branch instruction D is sent to theexecution unit for execution) then the information in the update historyshift register 1504 and an indication of whether the circular buffer wasupdated are stored in the data position pointed to by the write pointer2506 and then the write pointer 2506 is incremented to point to the nextdata position as shown in FIG. 25(B).

In some cases the indication of whether the circular buffer was updatedis a single bit which is set to a “1” if the circular buffer was updatedand a “0” if the circular buffer was not updated. For example, if aconditional branch instruction is sent to the execution unit forexecution (which causes an update to the circular buffer as a branchprediction is made) then the information in the update history shiftregister 1504 and a “1” are stored in the data position pointed to bythe write pointer 2506. If, however, a jump instruction is sent to theexecution unit for execution (which is a CTI that does not cause anupdate to the circular buffer as no branch prediction was made) then theinformation in the update history shift register 1504 and a “0” arestored in the data position pointed to by the write pointer 2506.

Each time a removal trigger event occurs (e.g. information from theexecution unit (EXU) indicating that a control transfer instruction hasbeen executed is received) the data elements in the data position 2502 ₀to 2502 ₄ pointed to by the read-pointer 2504 are popped off therestoration buffer 2500. This may be done by incrementing the readpointer 2504 to point to the next data position 2502 ₀ to 2502 ₄. Forexample, if the restoration buffer 2500 is as shown in FIG. 25(B), whena removal trigger event occurs (e.g. information is received from theEXU indicating that control transfer instruction A has been executed),then the read pointer 2504 is incremented to point to the next dataposition as shown in FIG. 25(C).

When a restoration trigger event occurs (e.g. an indication that amis-prediction has occurred is received) then the information in theupdate history shift register 1504 and value of the top pointer 1560 arereplaced based on data from the top data position (the data positionpointed to by the read pointer 2504) and the entries in the restorationbuffer 2500 are nullified. In particular, the information in the updatehistory shift register 1504 is replaced with the update history shiftregister information in the top data position of the restoration buffer;and the number of data positions of the restoration buffer 2500 thatindicate a branch prediction were made are counted and this count isused to update the top pointer 1560 (e.g. the top pointer may beincremented by this count).

This change to the top pointer 1560 causes the active data positions ofthe circular buffer 1502 to be altered so that a different set of datapositions of the circular buffer 1502 are used to determine the currentvalue of the main shift register (e.g. GHR) and check points. In otherwords it moves the active data positions back to what they were at theprevious point in time (e.g. before the mis-predicted instruction wasissued to the execution unit for execution). An example showing thecircular buffer 1502, top pointer 1560, update history shift register1504 and restoration buffer 2500 after a restoration event will bedescribed with reference to FIGS. 26(A)-26(B).

In this example restoration buffer 2500, each data position in therestoration buffer 2600 has C bits (for the update history shiftregister)+1 bit for the circular buffer update indicator. Where thereare M data positions in the restoration buffer the total number of bitsfor the restoration buffer 2500 is then M*(C+1). So, where C is 3, and Mis 16 the total number of bits to implement the restoration buffer 2300is only 64.

FIGS. 26(A)-26(B) show an example of the circular buffer 1502, toppointer 1560, update history shift register 1504 and restoration buffer2500 after a restoration event. In particular, in FIG. 26(A) the updatehistory shift register 1504 is equal to “001”, the top pointer 1560 isequal to “00011” (3), and the circular buffer 1502 is equal to“010100000100101100011101” meaning that the active data positions A₀ toA₁₁ of the circular buffer are data positions 4 to 14.

If a restoration event (e.g. a mis-prediction of instruction X)subsequently occurs then the update history shift register 1504 and toppointer 1560 are updated as shown in FIG. 26(B) based on the informationin the restoration buffer 2500 to restore them to what they were beforeinstruction X was sent to the execution unit for execution. Inparticular, the information in the update history shift register 1504 isreplaced with the update history shift register information in the topdata position (i.e. the data position pointed to by the read pointer2502). In the example of FIG. 26(A) the update history shift registerinformation in the top data position 2502 ₀ is “101” so after therestoration event the update history shift register 1504 is set to “101”as shown in FIG. 26(B).

The number of circular buffer update indicators is also counted and usedto restore the top pointer 1560 to its value prior to instruction Xbeing sent to the execution unit for execution. In the example of FIGS.26(A)-26(B) the restoration buffer has two data positions (2502 ₀ and2502 ₂) where the circular buffer update indicator is set indicatingthat two branch predictions (thus two updates to the circular buffer1502) have been made since before instruction X was issued to theexecution unit for execution. Accordingly the top pointer 1560 isrestored to its value prior to instruction X being sent to the executionunit for execution by adding two to the top pointer 1560. In particular,prior to the restoration event the top pointer was “00011” so to restorethe top pointer 1560 to its value prior to instruction X being sent tothe execution unit for execution the top pointer value “00011” isincremented by two to “00101” (5).

It can be seen from FIGS. 26(A)-26(B) that this changes the active datapositions of the circular buffer from data positions 4 to 14 back todata positions 6 to 16.

Once the update history shift register 1504 and top pointer 1560 havebeen restored the data in the restoration buffer 2500 is invalidated.This may involve setting the write pointer 2506 and read pointer 2504 topoint to the same data position indicating the restoration buffer 2500is empty.

FIG. 27 illustrates an example hardware structure 2700 for implementingthe shift register check pointing method described above with referenceto FIGS. 15 to 26. The hardware structure 2700 comprises the circularbuffer 1502, update history shift register 1504 and top pointer 1560described above. The hardware structure 2700 also comprises arestoration buffer 2702 which may be, for example, the restorationbuffer 2300 of FIGS. 23(A)-23(C) or the restoration buffer 2500 of FIGS.25(A)-25(C).

The hardware structure also comprises update logic 2704 for updating thecircular buffer 1502, update history shift register 1504, top pointer1560 and restoration buffer 2702 as described above. In particular, theupdate logic 2704 is configured to receive new data elements for themain shift register (e.g. GHR) and update the circular buffer 1502,update history shift register 1504, top pointer 1560 and restorationbuffer 2702 accordingly as described with reference to FIGS. 16-18, and23-26. For example, where the shift register being check pointed is aGHR the new data elements to be added to the GHR may be the predictedoutcome of a conditional branch instruction.

The hardware structure also comprises check point generation logic 2706for generating the check points and/or main shift register from thecircular buffer 1502, the update history shift register 1504 and the toppointer 1560 as described above with reference to FIGS. 19-22. Forexample, the check point generation logic 2706 may be configured toimplement one or more of the methods described with reference to FIGS.19 to 21.

The hardware structure 2700 may also comprise restoration logic 2708 forrestoring the update history shift register 1504 and top pointer 1560 toa previous point in time based on the information stored in therestoration buffer 2702 upon receiving notification of a restorationtrigger event (e.g. mis-prediction of a conditional branch instruction)as described above with reference to FIGS. 23-26.

For example, where the restoration buffer 2702 is configured to storecopies of the update history shift register 1504 and top pointer 1560 atparticular points in time (e.g. as described with reference to FIGS.23(A)-23(C)), when the restoration logic 2708 is notified of arestoration trigger event the restoration logic 2708 may be configuredto replace the update history shift register 1504 and top pointer 1560with the values stored in the restoration buffer 2702. Where, however,the restoration buffer 2702 is configured to store a copy of the updatehistory shift register 1504 and information indicating whether thecircular buffer 1502 was updated (e.g. as described with reference toFIGS. 24-26), when the restoration logic 2708 is notified of arestoration trigger event the restoration logic 2708 may be configuredto replace the update history shift register 1504 with the updatehistory shift register data stored in the restoration buffer 2702 andupdate the value of the top pointer 1560 based on the informationindicating whether the circular buffer 1502 was updated.

A first further example provides a hardware structure configured toderive one or more check points for a main shift register having apredetermined number of data positions, the hardware structurecomprising: an extended shift register comprising a data position foreach data position of the main shift register and an additional dataposition for each check point, the data positions of the extended shiftregister storing data elements most recently shifted onto the main shiftregister; an update history shift register comprising a data positionfor each check point, each data position of the update history registerstoring information indicating whether the extended shift register wasupdated in a same clock cycle as a particular check point trigger event;and check point generation logic configured to derive each check pointby selecting a subset of the data positions of the extended shiftregister based on the information stored in the update history shiftregister.

A second further example provides a method to derive one or more checkpoints for a main shift register having a predetermined number of datapositions, the method comprising: storing the predetermined number ofdata elements most recently shifted onto the main shift register in aplurality of data positions of an extended shift register; storing anadditional data element for each check point in an extra data positionof the extended shift register; storing information indicating whetherthe extended shift register was updated in a same clock cycle as aparticular check point trigger event in a data position of an updatehistory shift register; and deriving each check point by selecting asubset of the data positions of the extended shift register based on theinformation stored in the update history shift register.

A third further example provides a hardware structure to derive one ormore check points for a main shift register having a predeterminednumber of data positions and being restorable to a plurality of pointsin time, the hardware structure comprising: a circular buffer comprisinga data position for each data position of the main shift register, anadditional data position for each check point, and an additional dataposition for each of the plurality of points in time, the data positionsof the circular buffer storing data elements most recently shifted ontothe main shift register; a pointer configured to identify a plurality ofactive data positions of the circular buffer, the active data positionscomprising a subset of the data positions of the circular buffer storingthe data elements most recently written to the circular buffer; anupdate history shift register having a data position for each checkpoint, the data positions of the update history shift register storinginformation indicating whether the circular buffer was updated in a sameclock cycle as a particular check point trigger event; and check pointgeneration logic configured to derive each check point by selecting asubset of the active data positions based on the information stored inthe update history shift register.

A fourth further example provides a method to derive one or more checkpoints for a main shift register having a predetermined number of datapositions and being restorable to a plurality of periods of time, themethod comprising: storing the predetermined number of data elementsrecently shifted onto the main shift register in a plurality of datapositions of a circular buffer; storing an additional data element foreach check point in an extra data position of the circular buffer;storing an additional data element for each period of time in theplurality of periods of time in an extra data positions of the circularbuffer; storing an index to the circular buffer in a pointer, the indexidentifying active data positions of the circular buffer; storinginformation indicating whether the circular buffer was updated in a sameclock cycle as a particular check point trigger event in a data positionof an update history shift register; and deriving each check point byselecting a subset of the active data positions based on the informationstored in the update history shift register.

The methods described herein may be performed by a computer configuredwith software in machine readable form stored on a tangible storagemedium e.g. in the form of a computer program comprising computerreadable program code for configuring a computer to perform theconstituent portions of described methods or in the form of a computerprogram comprising computer program code means adapted to perform allthe steps of any of the methods described herein when the program is runon a computer and where the computer program may be embodied on acomputer readable storage medium. Examples of tangible (ornon-transitory) storage media include disks, thumb drives, memory cardsetc. and do not include propagated signals. The software can be suitablefor execution on a parallel processor or a serial processor such thatthe method steps may be carried out in any suitable order, orsimultaneously.

The term ‘processor’ and ‘computer’ are used herein to refer to anydevice, or portion thereof, with processing capability such that it canexecute instructions. The term ‘processor’ may, for example, includecentral processing units (CPUs), graphics processing units (GPUs orVPUs), physics processing units (PPUs), radio processing units (RPUs),digital signal processors (DSPs), general purpose processors (e.g. ageneral purpose GPU), microprocessors, any processing unit which isdesigned to accelerate tasks outside of a CPU, etc. Those skilled in theart will realize that such processing capabilities are incorporated intomany different devices and therefore the term ‘computer’ includes settop boxes, media players, digital radios, PCs, servers, mobiletelephones, personal digital assistants and many other devices.

Those skilled in the art will realize that storage devices utilized tostore program instructions can be distributed across a network. Forexample, a remote computer may store an example of the process describedas software. A local or terminal computer may access the remote computerand download a part or all of the software to run the program.Alternatively, the local computer may download pieces of the software asneeded, or execute some software instructions at the local terminal andsome at the remote computer (or computer network). Those skilled in theart will also realize that by utilizing conventional techniques known tothose skilled in the art that all, or a portion of the softwareinstructions may be carried out by a dedicated circuit, such as a DSP,programmable logic array, or the like.

The methods described herein may be performed by a computer configuredwith software in machine readable form stored on a tangible storagemedium e.g. in the form of a computer program comprising computerreadable program code for configuring a computer to perform theconstituent portions of described methods or in the form of a computerprogram comprising computer program code means adapted to perform allthe steps of any of the methods described herein when the program is runon a computer and where the computer program may be embodied on acomputer readable storage medium. Examples of tangible (ornon-transitory) storage media include disks, thumb drives, memory cardsetc and do not include propagated signals. The software can be suitablefor execution on a parallel processor or a serial processor such thatthe method steps may be carried out in any suitable order, orsimultaneously.

The hardware components described herein may be generated by anon-transitory computer readable storage medium having encoded thereoncomputer readable program code.

It is also intended to encompass software which “describes” or definesthe configuration of hardware that implements a module, functionality,component or logic described above, such as HDL (hardware descriptionlanguage) software, as is used for designing integrated circuits, or forconfiguring programmable chips, to carry out desired functions. That is,there may be provided a computer readable storage medium having encodedthereon computer readable program code for generating a processing unitconfigured to perform any of the methods described herein, or forgenerating a processing unit comprising any apparatus described herein.That is, a computer system may be configured to generate arepresentation of a digital circuit from definitions of circuit elementsand data defining rules for combining those circuit elements, wherein anon-transitory computer readable storage medium may have stored thereonprocessor executable instructions that when executed at such a computersystem, cause the computer system to generate a processing unit asdescribed herein. For example, a non-transitory computer readablestorage medium may have stored thereon computer readable instructionsthat, when processed at a computer system for generating a manifestationof an integrated circuit, cause the computer system to generate amanifestation of a processor of a receiver as described in the examplesherein or to generate a manifestation of a processor configured toperform a method as described in the examples herein. The manifestationof a processor could be the processor itself, or a representation of theprocessor (e.g. a mask) which can be used to generate the processor.

Memories storing machine executable data for use in implementingdisclosed aspects can be non-transitory media. Non-transitory media canbe volatile or non-volatile. Examples of volatile non-transitory mediainclude semiconductor-based memory, such as SRAM or DRAM. Examples oftechnologies that can be used to implement non-volatile memory includeoptical and magnetic memory technologies, flash memory, phase changememory, resistive RAM.

A particular reference to “logic” refers to structure that performs afunction or functions. An example of logic includes circuitry that isarranged to perform those function(s). For example, such circuitry mayinclude transistors and/or other hardware elements available in amanufacturing process. Such transistors and/or other elements may beused to form circuitry or structures that implement and/or containmemory, such as registers, flip flops, or latches, logical operators,such as Boolean operations, mathematical operators, such as adders,multipliers, or shifters, and interconnect, by way of example. Suchelements may be provided as custom circuits or standard cell libraries,macros, or at other levels of abstraction. Such elements may beinterconnected in a specific arrangement. Logic may include circuitrythat is fixed function and circuitry can be programmed to perform afunction or functions; such programming may be provided from a firmwareor software update or control mechanism. Logic identified to perform onefunction may also include logic that implements a constituent functionor sub-process. In an example, hardware logic has circuitry thatimplements a fixed function operation, or operations, state machine orprocess.

Any range or device value given herein may be extended or alteredwithout losing the effect sought, as will be apparent to the skilledperson.

It will be understood that the benefits and advantages described abovemay relate to one embodiment or may relate to several embodiments. Theembodiments are not limited to those that solve any or all of the statedproblems or those that have any or all of the stated benefits andadvantages.

Any reference to an item refers to one or more of those items. The term‘comprising’ is used herein to mean including the method blocks orelements identified, but that such blocks or elements do not comprise anexclusive list and an apparatus may contain additional blocks orelements and a method may contain additional operations or elements.Furthermore, the blocks, elements and operations are themselves notimpliedly closed.

The steps of the methods described herein may be carried out in anysuitable order, or simultaneously where appropriate. The arrows betweenboxes in the figures show one example sequence of method steps but arenot intended to exclude other sequences or the performance of multiplesteps in parallel. Additionally, individual blocks may be deleted fromany of the methods without departing from the spirit and scope of thesubject matter described herein. Aspects of any of the examplesdescribed above may be combined with aspects of any of the otherexamples described to form further examples without losing the effectsought. Where elements of the figures are shown connected by arrows, itwill be appreciated that these arrows show just one example flow ofcommunications (including data and control messages) between elements.The flow between elements may be in either direction or in bothdirections.

It will be understood that the above description of a preferredembodiment is given by way of example only and that variousmodifications may be made by those skilled in the art. Although variousembodiments have been described above with a certain degree ofparticularity, or with reference to one or more individual embodiments,those skilled in the art could make numerous alterations to thedisclosed embodiments without departing from the spirit or scope of thisinvention.

1. A hardware structure configured to derive one or more check pointsfor a main shift register, the check points being triggered by triggerevents, the hardware structure comprising: an extended shift registerhaving a plurality of data positions for storing data elements, theplurality of data positions including a first subset of data positionswhich represent the main shift register and an additional data positionfor each check point; an update history shift register having a dataposition for each check point, each data position of the update historyshift register storing information indicating whether the extended shiftregister was updated in a same clock cycle as a particular check pointtrigger event; and check point generation logic configured to deriveeach check point by selecting a subset of the plurality of datapositions of the extended shift register based on the information storedin the update history shift register.
 2. The hardware structure of claim1, wherein the selected subset of the plurality of data positions of theextended shift register for a particular check point can be offset fromthe first subset of data positions by none, one or more than one dataposition.
 3. The hardware structure of claim 2, wherein the check pointgeneration logic is configured to determine the offset from the firstsubset of data positions for a particular check point by evaluating theinformation stored in a number of relevant data positions of the updatehistory shift register
 4. The hardware structure of claim 3, whereineach check point represents the main shift register prior to a number ofcheck point trigger events, and the number of relevant data positionsfor a particular check point is equal to the number of check pointtrigger events for that check point.
 5. The hardware structure of claim3, wherein the offset is equal to a count of the relevant data positionsof the update history shift register that comprise informationindicating that the extended shift register was updated.
 6. The hardwarestructure of claim 2, wherein the check point generation logic isconfigured to derive a first check point that represents the main shiftregister prior to a most recent check point trigger event by:determining, in the check point generation logic, whether a first dataposition of the update history shift register comprises informationindicating that the extended shift register was updated; in response todetermining that the first data position of the update history shiftregister does not comprise information indicating that the extendedshift register was not updated, selecting, in the check point generationlogic, the first subset of data positions of the extended shiftregister; and in response to determining that the first data position ofthe update history shift register comprises information indicating thatthe extended shift register was updated, selecting, in the check pointgeneration logic, a subset of the plurality of data positions of theextended shift register that is offset from the first subset of datapositions by one data position.
 7. The hardware structure of claim 2,wherein the number of check points is at least two, and the check pointgeneration logic is configured to derive a second check point thatrepresents the main shift register prior to the two most recent checkpoint trigger events by: counting, in the check point generation logic,the number of the first two data positions of the update history shiftregister that comprise information indicating that the extended shiftregister was updated; and selecting, in the check point generationlogic, a subset of the plurality of data positions of the extended shiftregister that is offset from the first subset of data positions by thecount.
 8. The hardware structure of claim 1, further comprising updatelogic configured to, in each clock cycle: determine, in the updatelogic, whether a check point trigger event has occurred; in response todetermining that a check point trigger event has occurred, determine, inthe update logic, whether the extended shift register is updated in thecurrent clock cycle; in response to determining that the extended shiftregister is updated in the current clock cycle, shift, by the updatelogic, information onto the update history shift register indicating theextended shift register has been updated; and in response to determiningthat the extended shift register is not updated in the current clockcycle, shift, by the update logic, information onto the update historyshift register indicating the extended shift register has not beenupdated.
 9. The hardware structure of claim 1, further comprising arestoration buffer having a plurality of data positions, each dataposition storing a copy of the data elements of the extended shiftregister and a copy of the information of the update history shiftregister at a particular point in time.
 10. The hardware structure ofclaim 9, further comprising restoration logic, the restoration logicconfigured to, in response to receiving an indication that a restorationis to be performed, restore the extended shift register and the updatehistory shift register to a particular point in time using the copiesstored in the restoration buffer.
 11. The hardware structure of claim10, wherein the main shift register is a global history register andeach data element of the extended shift register indicates a predictedoutcome for a conditional branch instruction; and the indication that arestoration is to be performed is an indication that a conditionalbranch instruction was mis-predicted.
 12. The hardware structure ofclaim 1, wherein the main shift register is a global history registerand each data element of the extended shift register indicates apredicted outcome for a conditional branch instruction.
 13. The hardwarestructure of claim 12, wherein the check point trigger event is aninstruction being sent to an execution unit for execution.
 14. Aprocessor comprising the hardware structure as set forth in claim
 1. 15.An instruction fetch unit comprising the hardware structure as set forthin claim
 1. 16. A method for deriving one or more check points for amain shift register, the check points being triggered by trigger events,the method comprising: storing data elements in a plurality of datapositions of an extended shift register, the plurality of data positionsincluding a first subset of data positions which represent the mainshift register and an additional data position for each check point;storing information indicating whether the extended shift register wasupdated in a same clock cycle as a particular check point trigger eventin a data position of an update history shift register; and deriving, inhardware logic, each check point by selecting a subset of the pluralityof data positions of the extended shift register based on theinformation stored in the update history shift register.
 17. The methodof claim 16, wherein selecting, in the hardware logic, a subset of theplurality of data positions of the extended shift register for aparticular check point comprises selecting a subset of the plurality ofdata positions of the extended shift register that is offset from thefirst subset of data positions by none, one or more than one datapositions based on the information stored in the update history shiftregister.
 18. The method of claim 17, wherein the offset for aparticular check point is determined by evaluating, in the hardwarelogic, the information stored in a number of relevant data positions ofthe update history shift register.
 19. The method of claim 18, whereineach check point represents the main shift register prior to a number ofcheck point trigger events and the number of relevant data positions ofthe update history shift register is equal to the number of check pointtrigger events for that check point.
 20. The method of claim 18, whereinthe offset is equal to a count of the relevant data positions of theupdate history shift register that comprise information indicating thatthe extended shift register was updated.